3.4 I/O Pin Configuration

Pin Map | Input Channel Limits | Output Limits

Logic Levels Enabled : 1, Disabled: 0

Pin Map

Pins 1, 2 GND or Ground Input Electrical Limit: 0.5 A max

Pins 3, 4 VIN or Supply Voltage Input Electrical Limit: 3.0 → 5.5 V relative to GND, 0.5 A max

Pin 5 VCC or Interface Supply Voltage Set to the voltage of the logic between 1.8 and 5.5 V. The pin will draw current equal to sum of all interfacing pins Input Electrical Limit: -0.5 → +6.5 V, 100mA

Pin 6 RF Amplifier Enable Input Channel Input

Pin 7 Update Notice / DSR Output Channel Output

Pin 8 SPI MOSI Input

Pin 9 SPI MISO Output

Pin 10 SPI SCK Input

Pin 11 SPI SS, Slave Select Input

Pin 12 USART TX - MiniSatCom RX Input

Pin 13 USART RX - MiniSatCom TX Output

Pin 14 USART CTS Output

Pin 15 USART DTR Input

Pin 16 USART XCK Input

Pin 17 TWI SCI Input

Pin 18 TWI SDA Input / Output

Pin 19 Output 1 Output

Pin 20 Output 2 Output

3.4.1.1. Input Channel Definition

Logic level 0 (Low) Min: 0, Max: VCC * 0.35, Units: V

Logic level 1 (High) Min: VCC * 0.65, Max: VCC, Units: V

Current source/drain from VCC Min: 0, Max: 0.001, Units: A

Absolute voltage Min: -0.5, Max: VCC + 0.5, Units: V

3.4.1.2. Output Channel Definition

Logic level 0 (Low) Min: 0, Max: VCC * 0.35, Units: V

Logic level 1 (High) Min: VCC * 0.65, Max: VCC, Units: V

Current source/drain from VCC Min: -0.050, Max: 0.050, Units: A

Absolute voltage Min: -0.5, Max: VCC + 0.5, Units: V